1. Field of the Invention
This invention relates to a reset circuit that resets a high voltage circuit to which a high voltage generated by a voltage boosting circuit is applied.
2. Description of the Related Art
In an EEPROM (Electrically Erasable and Programmable Memory) such as a flash memory, electric charges are generally injected into a floating gate by providing a memory cell with a channel current in a programming operation while a high voltage is applied to a source of the memory cell. Also, when erasing the program, the high voltage is applied to a gate of the memory cell or a substrate to extract the electric charges injected into the floating gate to the gate or the substrate. A charge pump circuit to generate the high voltage is embedded in the EEPROM.
FIG. 7 is a block diagram showing circuits in the EEPROM as described above. The EEPROM is provided with a memory block 1 including a plurality of memory cells, analog circuit block 2 and a digital circuit block 3. Also, a power-on reset circuit 4 that detects power-on and power-down and generates a reset signal is provided. And a whole system of the EEPROM is reset in response to the reset signal.
The high voltage outputted from the charge pump circuit is applied to the memory block 1 and the analog circuit block 2 during the programming operation and the erasing operation. Transistors in the memory block 1 and analog circuit block 2 are made of high withstand voltage transistors that can withstand the high voltage. Therefore, there is no problem in applying the high voltage to the transistors while they are turned off. However, when the transistor is turned from an OFF state to an ON state to make a drain current flow while the high voltage is applied to its drain, a drain withstand voltage is reduced to cause a breakdown and thereby deterioration of the transistor is induced. Thus, in order to protect the transistors, the transistors are configured not to make the switching operation while the high voltage is applied to them.
The EEPROM incorporating the charge pump circuit is disclosed in Japanese Patent Application Publication No. 2004-135414, for example.
When a power-down occurs during the programming operation or the erasing operation, however, the power-on reset circuit 4 is put into operation to reset the whole system in a stroke. At that time, although the operation of the charge pump circuit is stopped, the high voltage is not reduced immediately. As a result, there is a possibility that a reset transistor for resetting is turned on while the high voltage is applied and the reset transistor is thereby deteriorated.